Document Type

Article

Publication Date

3-2010

Publication Title

IEICE Transactions On Electronics

Abstract

This paper presents the implementation of a novel parallel FFT algorithm on SmartCell, a coarse-grained reconfigurable architecture, which is targeted on data streaming applications. The proposed FFT algorithm achieves balanced workload and memory requirement among the computational units, while maintaining optimized data flow at low configuration and communication cost. The proposed parallel FFT algorithm is then mapped onto the SmartCell prototype device with 64 processing elements. Results show that the parallel FFT implementation on SmartCell is about 14.9 and 2.7 times faster than network-on-chip (NoC) and Morphosys, respectively. The implementation also shows about 3.6 times better energy efficiency when comparing with the pipelined FFT implementations on FPGA.

Issue

3

First Page Number

407

Last Page Number

415

DOI

10.1587/transele.E93.C.407

Publisher Statement

© 2010, IEICE - Institute of Electronics, Information and Comunication Engineers. Available on publisher's site at http://dx.doi.org/10.1109/ASAP.2009.33.

Share

 
COinS