A regular RAM module is designed for use with one system. This project designed a memory arbiter in Verilog that allows for more than one system to use a single DDR3 RAM module in a controlled manner. The arbiter uses fixed priority scheme with an additional timeout feature to avoid starvation. The design was verified in simulation and validated on a Xilinx ML605 evaluation board with a Virtex-6 FPGA.

• This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.

Creator

• Esa, Arten Ahmed-Hussein
• Myers, Bryan James

Contributors

• Kaushansky, David
• Fluet, Michael
• Eng, Stephen

Publisher

• Worcester Polytechnic Institute

Identifier

• E-project-042513-153905

Advisor

• McNeill, John A.
• Duckworth, R. James

Year

• 2013

Sponsor

• Teradyne

Date created

• 2013-04-25

Resource type

• Major Qualifying Project

Major

• Electrical & Computer Engineering

Rights statement

• In Copyright