Student Work

Modular Redundancy for Robust Soft IP-Cores

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This project successfully implements a triple modular redundant system on an Altera field-programmable gate array, FPGA, development board for General Dynamics C4 Systems. The system implements a simple counting program simultaneously on three Altera Nios II soft IP-core CPUs; and has an error detecting voting scheme to catch errors, disable faulty CPUs, pass through good signals between the CPUs and the peripherals, and reset the system if it is compromised.

  • This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.
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  • E-project-042512-230610
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Year
  • 2012
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Date created
  • 2012-04-25
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Permanent link to this page: https://digital.wpi.edu/show/w95052009