Faculty Advisor or Committee Member
McNeill, John A.
Faculty Advisor or Committee Member
Guler, Ulkuhan
Faculty Advisor or Committee Member
Coln, Michael
Sponsor
National Science Foundation; Analog Devices Inc; Allegro MicroSystems LLC
Identifier
2801
Abstract
Nowadays, Multi-GHz analog-to-digital converters (ADCs) are becoming more and more popular in radar systems, software-defined radio (SDR) and wideband communications, because they can realize much higher operation speed through using many interleaved sub-ADCs to relax ADC sampling rates. Although the time interleaved ADC has some issues such as gain mismatch, offset mismatch and timing skew between each ADC channel, these deterministic errors can be solved by previous works such as digital calibration technique. However, time-interleaved ADCs require a precise sample clock to achieve an acceptable effective-numberof-bits (ENOB) which can be degraded by jitter in the sample clock. The clock generation circuits presented in this work achieves sub-picosecond jitter performance in 180nm CMOS which is suitable for time-interleaved ADC. Two different test chips were fabricated in 180nm CMOS to investigate the low jitter design technique. The low jitter delay line in two chips were designed in two different ways, but both of them utilized the low jitter design technique. In first test chip, the measured RMS jitter is 0.1061ps for each delay stage. The second chip uses the proposed low jitter Delay-Locked Loop can work from 80MHz to 120MHz, which means it can provide the time interleaved ADC with 2.4GHz to 3.6GHz low jitter sample clock, the measured delay stage jitter performance in second test chip is 0.1085ps.
Publisher
Worcester Polytechnic Institute
Degree Name
PhD
Department
Electrical & Computer Engineering
Project Type
Dissertation
Date Accepted
2019-07-30
Copyright Statement
All authors have granted to WPI a nonexclusive royalty-free license to distribute copies of the work. Copyright is held by the author or authors, with all rights reserved, unless otherwise noted. If you have any questions, please contact wpi-etd@wpi.edu.
Accessibility
Unrestricted
Repository Citation
Gong, J. (2019). Sub-Picosecond Jitter Clock Generation for Time Interleaved Analog to Digital Converter. Retrieved from https://digitalcommons.wpi.edu/etd-dissertations/557
Subjects
Clock signal; Delay-locked loop; Analog-to-digital converters