Faculty Advisor or Committee Member

John McNeill, Advisor

Faculty Advisor or Committee Member

Andrew Klein, Committee Member

Faculty Advisor or Committee Member

Stephen Bitar, Committee Member

Identifier

etd-042810-191950

Abstract

As the use of digital systems continues to grow, there is an increasing need to convert analog information into the digital domain. Successive Approximation Register (SAR) analog-to-digital converters are used extensively in this regard due to their high resolution, small die area, and moderate conversion speeds. However, capacitor mismatch within the SAR converter is a limiting factor in its accuracy and resolution. Without some form of calibration, a SAR converter can only reasonably achieve an accuracy of 10 bits. The Split-ADC technique is a digital, deterministic, background self-calibration algorithm that can be applied to the SAR converter. This thesis describes the circuit design and physical implementation of a novel 16-bit 1MS/s SAR analog-to-digital converter for use with the Split-ADC calibration algorithm. The system was designed using the Jazz 0.18um CMOS process, successfully operates at 1MS/s, and consumes a die area of 1.2mm2. The calibration algorithm was applied, showing an improvement in the overall accuracy of the converter.

Publisher

Worcester Polytechnic Institute

Degree Name

MS

Department

Electrical & Computer Engineering

Project Type

Thesis

Date Accepted

2010-04-28

Accessibility

Unrestricted

Subjects

ADC, Circuit design, Calibration, SAR

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