Faculty Advisor or Committee Member

Professor John McNeill, Advisor

Faculty Advisor or Committee Member

Professor D. Richard Brown, Committee Member

Faculty Advisor or Committee Member

Professor Stephen Bitar, Committee Member

Identifier

etd-011013-081923

Abstract

In this MS thesis, a redundant flash analog-to-digital converter (ADC) using a ``Split-ADC' calibration structure and lookup-table-based correction is presented. ADC input capacitance is minimized through use of small, power efficient comparators; redundancy is used to tolerate the resulting large offset voltages. Correction of errors and estimation of calibration parameters are performed continuously in the background in the digital domain. The proposed flash ADC has an effective-number-of-bits (ENOB) of 6-bits and is designed for a target sampling rate of 1Gs/s in 180nm CMOS. The calibration algorithm described has been simulated in MATLAB and an FPGA implementation has been investigated.

Publisher

Worcester Polytechnic Institute

Degree Name

MS

Department

Electrical & Computer Engineering

Project Type

Thesis

Date Accepted

2013-01-10

Accessibility

Unrestricted

Subjects

Calibration, Flash, ADC

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