Faculty Advisor or Committee Member

Brigitte Servatius, Advisor

Identifier

etd-0430103-155731

Abstract

A Dual-Eulerian graph is a plane multigraph G that contains an edge list which is simultaneously an Euler tour in G and an Euler tour in the dual of G. Dual-Eulerian tours play an important role in optimizing CMOS layouts of Boolean functions. When circuits are represented by undirected multigraphs the layout area of the circuit can be optimized through finding the minimum number of disjoint dual trails that cover the graph. This paper presents an implementation of a polynomial time algorithm for determining whether or not a plane multigraph is Dual-Eulerian and for finding the Dual-Eulerian trail if it exists.

Publisher

Worcester Polytechnic Institute

Degree Name

MS

Department

Mathematical Sciences

Project Type

Thesis

Date Accepted

2003-04-30

Accessibility

Unrestricted

Subjects

Dual Eulerian Graphs, VLSI

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