Faculty Advisor

McNeill, John A

Abstract

The design of a low-power 12-bit 100MSps pipeline analog-to-digital converter (ADC) with open-loop residue amplification using the novel "Split-ADC" architecture is described. The choice of a 12b 100MSps specification targets medical applications such as portable ultrasound. For a representative ADC such as the ADS5270, the figure of merit (FOM) is approximately 1pJ/step and the power dissipation is 113mW. The use of an open-loop residue amplifier resulted in a FOM of 0.571pJ/step and a power dissipation of 11.2mW.

Publisher

Worcester Polytechnic Institute

Date Accepted

February 2008

Major

Electrical and Computer Engineering

Project Type

Major Qualifying Project

Accessibility

Unrestricted

Advisor Department

Electrical and Computer Engineering

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