Faculty Advisor

Sunar, Berk

Abstract

The goal of this project, sponsored by General Dynamics C4 Systems, is to evaluate proprietary FPGA technology developed by Achronix Semiconductor Corporation and its effectiveness using a 128-bit, one clock cycle multiplier in a finite field, GF(2128), as a test application. The testing will determine if there is a significant increase in speed that can be achieved by simple modifications of existing synchronous HDL designs using three metrics: number of LUTs, number of registers, and clock speed.

Publisher

Worcester Polytechnic Institute

Date Accepted

April 2008

Major

Electrical and Computer Engineering

Project Type

Major Qualifying Project

Accessibility

Unrestricted

Advisor Department

Electrical and Computer Engineering

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