The goal of this work was to design a pipeline analog to digital converter that can be calibrated and corrected in the digital domain. The scope of this work included the design, simulation and layout of major analog design blocks. The design uses an open loop gain stage to reduce power consumption, increase speed and relax small process size design requirements. These nonlinearities are corrected using a digital correction algorithm implemented in MATLAB.

• This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.

Creator

• Thet, K Zin
• Anundson, Karen A
• Crasso, Anthony W

Publisher

• Worcester Polytechnic Institute

Identifier

• E-project-031111-010549

Advisor

• McNeill, John A.

Year

• 2011

Date created

• 2011-03-11

Resource type

• Major Qualifying Project

Major

• Electrical & Computer Engineering

Rights statement

• In Copyright