Faculty Advisor

McNeill, John A.

Abstract

The goal of this work was to design a pipeline analog to digital converter that can be calibrated and corrected in the digital domain. The scope of this work included the design, simulation and layout of major analog design blocks. The design uses an open loop gain stage to reduce power consumption, increase speed and relax small process size design requirements. These nonlinearities are corrected using a digital correction algorithm implemented in MATLAB.

Publisher

Worcester Polytechnic Institute

Date Accepted

March 2011

Major

Electrical and Computer Engineering

Project Type

Major Qualifying Project

Accessibility

Unrestricted

Advisor Department

Electrical and Computer Engineering

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