Faculty Advisor

Eisenbarth, Thomas

Project Center

MITRE-Bedford, Massachusetts


The power consumption of an FPGA’s routing network dominates the instantaneous power consumption of the device. A model for the routing network would therefore be useful for simulating the instantaneous power of the device. The goal of this project is to develop such a model, relating the power consumption of the routing network to the length of each net. This model will be integrated with power simulation tools in the Power Side-Channel Attack Risk Evaluator (PSCARE) to give a more accurate power simulation for FPGAs. Preliminary testing on the model shows that it can correctly simulate a modified PSCARE power simulation.


Worcester Polytechnic Institute

Date Accepted

January 2016


Electrical and Computer Engineering

Project Type

Major Qualifying Project



Advisor Department

Electrical and Computer Engineering

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