Faculty Advisor

Huang, Xinming

Faculty Advisor

McNeill, John A.

Abstract

The project presents a memory arbiter system capable of allowing two systems to communicate to the same DDR3 SDRAM memory. The arbiter was designed using Verilog, implemented using Xilinx Integrated Software Environment (ISE) and validated using iSim and ChipScope. The final design is implemented on a Virtex 6 FPGA chip. The arbiter can achieve a maximum performance of around 50 Gb/s, with the two systems reaching transfer rates of 25 Gb/s.

Publisher

Worcester Polytechnic Institute

Date Accepted

March 2012

Major

Electrical and Computer Engineering

Project Type

Major Qualifying Project

Accessibility

Unrestricted

Advisor Department

Electrical and Computer Engineering

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