Faculty Advisor

Bitar, Stephen John

Faculty Advisor

Brown, David C.

Abstract

The purpose of this project was to design a parallel digital circuit that performs neural network (NN) calculations more efficiently than traditional software implementations, by taking advantage of the NN's inherent parallel structure. User interfaces for NN training and testing were developed. Tic-Tac-Toe position evaluation was used as a test domain. Testing showed that the parallel hardware NN decreased the number of required clock cycles by an order of magnitude.

Publisher

Worcester Polytechnic Institute

Date Accepted

May 2010

Major

Computer Science

Major

Electrical and Computer Engineering

Project Type

Major Qualifying Project

Accessibility

Unrestricted

Advisor Department

Electrical and Computer Engineering

Advisor Department

Computer Science

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