This paper discusses the design of a 16-bit 10MHz pipeline Analog to Digital Converter (ADC) using the "Split ADC architecture". A system and circuit level design of each component of the ADC was created in Cadence. Features of the ADC were simulated in Matlab to test and examine its basic functionality. Transient analysis of the system level design was conducted to verify the performance of the ADC. Methods to correct non-linearities were identified and investigated.

• This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.

Creator

• Nair, Abhilash

Publisher

• Worcester Polytechnic Institute

Identifier

• E-project-101507-105824

Advisor

• McNeill, John A.

Year

• 2007

Date created

• 2007-10-15

Resource type

• Major Qualifying Project

Major

• Electrical & Computer Engineering

Rights statement

• In Copyright