Faculty Advisor

McNeill, John A

Abstract

This paper discusses the design of a 16-bit 10MHz pipeline Analog to Digital Converter (ADC) using the "Split ADC architecture". A system and circuit level design of each component of the ADC was created in Cadence. Features of the ADC were simulated in Matlab to test and examine its basic functionality. Transient analysis of the system level design was conducted to verify the performance of the ADC. Methods to correct non-linearities were identified and investigated.

Publisher

Worcester Polytechnic Institute

Date Accepted

October 2007

Major

Electrical and Computer Engineering

Project Type

Major Qualifying Project

Accessibility

Unrestricted

Advisor Department

Electrical and Computer Engineering

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