This paper focuses on real-time pedestrian detection using the Histograms of Oriented Gradients (HOG) feature descriptor algorithm on a Field Programmable Gate Array. To achieve real- time pedestrian recognition on embedded systems, hardware architecture for HOG feature extraction is proposed. In order to reduce computational complexity toward efficient hardware architecture, this paper proposes several methods to simplify the computation of the HOG feature descriptor. The architecture is proposed on a Xilinx Zynq-7000 SoC using Verilog HDL to evaluate the real-time performance. This implementation processes image data at twice the pixel rate of similar software simulations and significantly reduces resource utilization while maintaining high detection accuracy.

• This report represents the work of one or more WPI undergraduate students submitted to the faculty as evidence of completion of a degree requirement. WPI routinely publishes these reports on its website without editorial or peer review.

Creator

• MacDowell, William David
• Duan, Jiye

Publisher

• Worcester Polytechnic Institute

Identifier

• E-project-043014-124022

Advisor

• Huang, Xinming

Year

• 2014

Sponsor

• MathWorks

Date created

• 2014-04-30

Resource type

• Major Qualifying Project

Major

• Electrical & Computer Engineering

Rights statement

• In Copyright