Faculty Advisor

Huang, Xinming

Center

MITRE / Mitre Corporation

Abstract

This project is sponsored by MITRE Corporation to develop a scalable and reusable control plane architecture for VLSI design. The main goal of this project is to develop a communication platform for a wide range of applications to reduce the development and testing time associated with the design of a interconnect system. Thorough research has been conducted in the area of network-on-chip designs that are suitable for these types of applications. The necessary components are built and verified in hardware description language. The deliverable components are packaged as reusable and parameterized SystemVerilog code.

Publisher

Worcester Polytechnic Institute

Date Accepted

October 2012

Major

Electrical and Computer Engineering

Project Type

Major Qualifying Project

Accessibility

Unrestricted

Advisor Department

Electrical and Computer Engineering

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