Faculty Advisor

Sunar, Berk

Abstract

This project successfully implements a triple modular redundant system on an Altera field-programmable gate array, FPGA, development board for General Dynamics C4 Systems. The system implements a simple counting program simultaneously on three Altera Nios II soft IP-core CPUs; and has an error detecting voting scheme to catch errors, disable faulty CPUs, pass through good signals between the CPUs and the peripherals, and reset the system if it is compromised.

Publisher

Worcester Polytechnic Institute

Date Accepted

April 2012

Major

Electrical and Computer Engineering

Project Type

Major Qualifying Project

Accessibility

Unrestricted

Advisor Department

Electrical and Computer Engineering

Share

COinS