Faculty Advisor

Clancy, Edward A.

Center

MIT Lincoln Laboratory-Lexington, Massachusetts

Abstract

To extract data from highly sophisticated sensor networks, algorithms derived from graph theory are often applied to raw sensor data. Embedded digital systems are used to apply these algorithms. A common computation performed in these algorithms is finding the product of two sparsely populated matrices. When processing a sparse matrix, certain optimizations can be made by taking advantage of the large percentage of zero entries. This project proposes an optimized algorithm for performing sparse matrix multiplications in an embedded system and investigates how a parallel architecture constructed of multiple processors on a single Field-Programmable Gate Array (FPGA) can be used to speed up computations.

Publisher

Worcester Polytechnic Institute

Date Accepted

October 2007

Major

Electrical and Computer Engineering

Project Type

Major Qualifying Project

Accessibility

Unrestricted

Advisor Department

Electrical and Computer Engineering

Project Center

MIT Lincoln Laboratory-Lexington, Massachusetts

Your accessibility may vary due to other restrictions.

Share

COinS