Faculty Advisor

Eisenbarth, Thomas

Project Center

MITRE-Bedford, Massachusetts


While unknown to most people, hardware implementation attacks provide a serious adversary for systems that contain sensitive data. Mission critical information can be extracted from a design with little effort from an attacker when they have access to the physical hardware. Thus designers try to mitigate this problem by using unique countermeasures styles. This work presents the first practical differential power analysis security evaluation of a countermeasure style called t-private logic. A PRESENT block cipher S-Box was implemented on a Virtex 5 FPGA as a reference platform. Both hardware and simulated power traces were collected. Statistical analyses were performed (CPA and Correlation enhanced collision attack) and our results revealed a first-order side channel attack vulnerability.


Worcester Polytechnic Institute

Date Accepted

November 2014


Electrical and Computer Engineering

Project Type

Major Qualifying Project



Advisor Department

Electrical and Computer Engineering

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