Faculty Advisor

Bitar, Stephen J.


Allegro Microsystems, Inc., of Worcester, MA, has traditionally simulated top-level mixed signal integrated circuit designs using SPICE models running at the lowest abstraction (transistor) level. This method of simulation, although extremely accurate, is inherently time consuming and swamps system resources. In some cases, larger circuit designs have not been simulated in their entirety due to system limitations. In an effort to decrease simulation time, Verilog-A modeling is proposed as a viable solution to the problem. In a test case, an existing chip with known electrical characteristics is reduced to a Verilog-A model, simulated, and the results compared to SPICE. Preliminary results show that simulation time can be reduced by a factor of 200 without sacrificing critical electrical characteristics. Further testing is needed to verify the conversion process as a whole, as well as to generate the required comfort level among circuit designers. Recommendations for adopting Verilog-A modeling solutions for future circuit designs are proposed.


Worcester Polytechnic Institute

Date Accepted

January 2001


Electrical Engineering

Project Type

Major Qualifying Project


Restricted-WPI community only

Advisor Department

Electrical and Computer Engineering