Cryptographic algorithm agility, i.e., the capability to switch between several encryption algorithms, has become a desirable feature due to the algorithm-independent design paradigm of modern security protocols. This MQP describes the design and implementation of an algorithm-agile cryptographic co-processor board. The core of the board is an FPGA, which can be dynamically configured with a variety of block ciphers. The FPGA is capable of data encryption at high speeds through an ISA bus interface. The board contains a Ram with an algorithm library, i.e., a collection of FPGA configuration files. The library can be updated during operation.
Worcester Polytechnic Institute
Major Qualifying Project
Access to this report is limited to members of the WPI community. Please contact a project advisor or their department to request access
Restricted-WPI community only
Electrical and Computer Engineering