Faculty Advisor

Paar, Christof

Abstract

Cryptographic algorithm agility, i.e., the capability to switch between several encryption algorithms, has become a desirable feature due to the algorithm-independent design paradigm of modern security protocols. This MQP describes the design and implementation of an algorithm-agile cryptographic co-processor board. The core of the board is an FPGA, which can be dynamically configured with a variety of block ciphers. The FPGA is capable of data encryption at high speeds through an ISA bus interface. The board contains a Ram with an algorithm library, i.e., a collection of FPGA configuration files. The library can be updated during operation.

Publisher

Worcester Polytechnic Institute

Date Accepted

January 1999

Major

Electrical Engineering

Project Type

Major Qualifying Project

Accessibility

Restricted-WPI community only

Advisor Department

Electrical and Computer Engineering

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