Faculty Advisor

McNeill, John A.

Abstract

The design of a 16-bit 10MHz pipelined Analog to Digital Converter (ADC) using the Split ADC architecture is discussed. This paper Work includes system level and circuit level simulations of the analog subsystem, and future work to be done.

Publisher

Worcester Polytechnic Institute

Date Accepted

January 2007

Major

Electrical and Computer Engineering

Project Type

Major Qualifying Project

Accessibility

Restricted-WPI community only

Advisor Department

Electrical and Computer Engineering

Advisor Program

Electrical and Computer Engineering

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