Faculty Advisor

Clancy, Edward A.

Faculty Advisor

Clements, Kevin A.

Abstract

This project was done in conjunction with MIT Lincoln Laboratory to upgrade the Air Traffic Control System's Mode S secondary radar (MSSR). The group designed a digital down-converter (DDC) and a monopulse processor, two portions of the Mode S radar receiver, on a field programmable gate array (FPGA). The FPGA uses programmable architecture available from Xilinx and has approximately 3 million gates. Each DDC occupied only 3% of the FPGA's resources and the monopulse processor occupied 14%.

Publisher

Worcester Polytechnic Institute

Date Accepted

January 2003

Major

Electrical Engineering

Project Type

Major Qualifying Project

Accessibility

Restricted-WPI community only

Advisor Department

Electrical and Computer Engineering

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