Clancy, Edward A.
Clements, Kevin A.
MIT Lincoln Laboratory
This project was done in conjunction with MIT Lincoln Laboratory to upgrade the Air Traffic Control System's Mode S secondary radar (MSSR). The group designed a digital down-converter (DDC) and a monopulse processor, two portions of the Mode S radar receiver, on a field programmable gate array (FPGA). The FPGA uses programmable architecture available from Xilinx and has approximately 3 million gates. Each DDC occupied only 3% of the FPGA's resources and the monopulse processor occupied 14%.
Worcester Polytechnic Institute
Major Qualifying Project
Access to this report is limited to members of the WPI community. Please contact a project advisor or their department to request access
Restricted-WPI community only
Electrical and Computer Engineering