Faculty Advisor

Duckworth, R. James

Faculty Advisor

McNeill, John A.

Abstract

A regular RAM module is designed for use with one system. This project designed a memory arbiter in Verilog that allows for more than one system to use a single DDR3 RAM module in a controlled manner. The arbiter uses fixed priority scheme with an additional timeout feature to avoid starvation. The design was verified in simulation and validated on a Xilinx ML605 evaluation board with a Virtex-6 FPGA.

Publisher

Worcester Polytechnic Institute

Date Accepted

April 2013

Major

Electrical and Computer Engineering

Project Type

Major Qualifying Project

Accessibility

Unrestricted

Advisor Department

Electrical and Computer Engineering

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